1. Field of the Invention
This invention relates to the layout of printed and integrated circuits and particularly to the routing of clock signals. More particularly, it relates to the distribution of clock signals in large integrated circuits.
2. Description of the Related Art
Large circuits such as Application Specific Integrated Circuits (ASIC) require the distribution of clock signals from a single clock driver source to each clocked element (sink). The skew, i.e., unequal delay times, of the clock from the source to the sinks has a deleterious effect on the performance of the entire circuit. Since large integrated circuits such as ASICs include numerous clocked elements, into the tens or even hundreds of thousands, it is important to design the clock circuitry so as to minimize the skew.
Due to the narrow width of conductors in large scale integrated circuits, a clock network must meet electromigration reliability rules. The clock network must be capable of being analyzed by using industry standards of extraction and analysis tools. Other factors impacting the design are implementation with industry standard circuit libraries and EDA (Engineering Design Automation) tools and low impact on the chip size and performance.
Prior art clock distribution networks sometimes use a package routing layer. The package routing layer usually has very little sheet resistivity so the clock signal can be distributed throughout the package. This approach is not available for those designs where the package does not include routing layers. It can also be costly to implement due to the routing customization of the specific application. This technique does not address the problems of local clock distribution.
xe2x80x9cHxe2x80x9d or xe2x80x9cIxe2x80x9d tree methods, a form of balanced routing to achieve low skew, depends on symmetric placement of clocked elements in the integrated circuit. Some applications may contain some regular structures that are symmetrical such as in a microprocessor, but VLSI applications are often asymmetrical. This prior art approach also uses wide xe2x80x9cHxe2x80x9d or xe2x80x9cIxe2x80x9d structures at the global level with increases power consumption and increases the complexity of the analysis.
Grid structures have the disadvantage of additional wiring to form the grid and larger power consumption. It requires a significant amount of wiring, especially when multiple clock domains must be driven which increases the chip size.
Methods which demand a large amount of wiring increase the net capacitance of the distribution and need additional power. The electromigration effect is increased with increases in power.
This invention is a method of designing a low skew clock distribution system for circuit layouts containing clocked elements, especially very large scale integrated circuits (VLSI). Although it is applicable and useful in any circuit layout utilizing distributed signals, the description is especially applicable to VLSI and ASIC in particular. The faster the circuit elements, the more necessary a balanced clock distribution scheme.
The method disclosed maximizes VLSI performance due to the low skew. It also minimizes the development time and cost because it can be implemented with industry standard circuit libraries and EDA tools.
In accordance with the invention, local clock distribution networks are designated within regions in which a circuit layout is divided. Each local clock distribution network contains a local clock buffer which is coupled to the clocked circuit elements within the region by a minimum length path. A global clock distribution network is generated to couple the local clock buffers to the clock source by using serially connected buffers along equidistant paths.